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CREATED:20251213T122847Z
LAST-MODIFIED:20251213T122847Z
DTSTAMP:20260817T234113Z
UID:1786999273@tuc.gr
SUMMARY:"The Renaissance of Distributed Shar
 ed Memory Systems" by Dr. Chloe Alve
 rti
LOCATION:Λ - Κτίριο Επιστημών/ΗΜΜΥ, 141Π-98
DESCRIPTION:https://www.ece.tuc.gr/el/katalogos-
 ekdiloseon?tx_tucevents2_tuceventsdi
 splay%5Baction%5D=show&tx_tucevents2
 _tuceventsdisplay%5Bcontroller%5D=Ev
 ent&tx_tucevents2_tuceventsdisplay%5
 Bevent%5D=8208&cHash=126a756365319aa
 ddd58c7c431e0bb47\nTitle\n The Renai
 ssance of Distributed Shared Memory 
 Systems\n  \n Abstract\n Distributed
  Shared Memory (DSM), a long-standin
 g systems vision, is being revisited
  as emerging interconnects such as C
 XL offer low-latency, cache-coherent
  memory access across the nodes of a
  rack. This technological shift invi
 tes us to rethink core systems inter
 faces: how processes and state move 
 across machines, how shared-memory a
 pplications scale in distributed set
 tings, and how DSM systems remain re
 silient in the presence of faults. P
 rogress will require advances in bot
 h software and hardware—and often th
 eir co-design. This talk highlights 
 two recent developments along this p
 ath. CXLfork, a system-software mech
 anism, introduces a zero-serializati
 on, near-zero-copy remote fork by ch
 eckpointing process state directly i
 nto shared CXL memory. It enables cl
 uster-wide state deduplication, fine
 -grained state tiering, and near-loc
 al fork latency, unlocking rapid pro
 cess scaling across the rack – essen
 tial for highly concurrent workloads
  such as serverless functions. At th
 e hardware layer, PhasedStore addres
 ses a fundamental vulnerability of c
 ache-coherent DSM systems: resilienc
 e to node failures. In such systems,
  node crashes can silently lose dirt
 y shared data buffered in private CP
 U caches. PhasedStore mitigates this
  risk by supporting high-performance
  write-through coherence protocols t
 hat ensure dirty data is propagated 
 into a fault-tolerant domain, all wh
 ile preserving the widely adopted To
 tal Store Order (TSO) memory consist
 ency model. Together, these developm
 ents outline a path toward practical
 , performant, and fault-tolerant dis
 tributed shared memory.\n  \n \n Abo
 ut the Speaker\n Chloe Alverti recei
 ved her Diploma in Electrical and Co
 mputer Engineering from the National
  Technical University of Athens in 2
 014 and her Ph.D. in Computer Engine
 ering from the same institution in 2
 022.  From 2023 to 2025 she was a po
 st-doctoral researcher at the CS dep
 artment of the University of Illinoi
 s (Urbana-Champaign). Prior and duri
 ng her PhD studies, she has held res
 earch positions at Chalmers Universi
 ty of Technology, the University of 
 Wisconsin–Madison, and she also spen
 t a year at ZeroPoint Technologies, 
 an academic spin-off. Her research i
 nterests span operating systems, com
 puter architecture and hardware–soft
 ware co-design. Her core expertise l
 ies in translating hardware technolo
 gical shifts into system software in
 novations and for over a decade her 
 work has centered on memory systems.
  She is a recipient of multiple HiPE
 AC and best paper awards, and her re
 cent work on process “teleportation”
 ’ over CXL fabrics received the Best
  Paper Award at ASPLOS 2025.\n
STATUS:CONFIRMED
ORGANIZER;RSVP=FALSE;CN=TUC;CUTYPE=TUC:mailto:webmaster@tuc.gr
DTSTART:20251217T130000
DTEND:20251217T140000
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